Z51F3220FNX Datasheet, PDF (188/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.12.2 USI0 UART Mode
The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial
communication device. The main features are listed below.
- Full Duplex Operation (Independent Serial Receive and Transmit Registers)
- Asynchronous or Synchronous Operation
- Baud Rate Generator
- Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits
- Odd or Even Parity Generation and Parity Check Supported by Hardware
- Data OverRun Detection
- Framing Error Detection
- Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
- Double Speed Asynchronous communication mode
USI0 has three main parts of clock generator, Transmitter and receiver. The clock generation logic consists of
synchronization logic for external clock inut used by synchronous or SPI slave operation, and the baud rate
generator for asynchronous or master (synchronous or SPI) operation.
The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for
handling different serial frame formats. The write buffer allows continuous transfer of data without any delay
between frames. The receiver is the most complex part of the UART module due to its clock and data recovery
units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the receiver
includes a parity checker, a shift register, a two-level receive FIFO (USI0DR) and control logic. The receiver
supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors.
PS029902-0212
PRELIMINARY
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