Z51F3220FNX Datasheet, PDF (226/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.3 USI1 UART Block Diagram
Master
SCK1
ACK
Control
2
USI1MS[1:0]
To interrupt
block
SCLK
(fx: System clock)
USI1BD
Baud Rate Generator
DBLS1
WAKEIE1
RXCIE1
At Stop mode
Clock
Sync Logic
WAKE1
Low level
detector
RXC1
I
RXD1
M
U
Rx
Control
X
LOOPS 1 ^RXE1
Data
Recovery
N
Clock
T
Recovery
E
USI1S[2:0]
R
N
3
A
Receive Shift Register
M
L
(RXSR)
U
X
B
U
DOR1/PE 1/FE1
2
S
Checker
USI1 DR[0], USI1RX8 [0], (Rx) USI1MS[1:0 ]
L
USI1SB
USI1 DR[1], USI1RX8 [1], (Rx)
I
N
TXE1
Stop bit
Generator
USI1P[1:0]
2
USI1S[2:0]
USI1MS[1:0]
E
3
2
TXD1
Tx
Control
Parity
Generator
M
Transmit Shift Register
(TXSR)
U
X
Clear
INT_ACK
TXC1
Empty signal
DRE1
USI1DR, USI1 TX8 , (Tx)
TXCIE1
DRIE1
To interrupt
block
Figure 11.78 USI1 UART Block Diagram
PS029902-0212
PRELIMINARY
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