Z51F3220FNX Datasheet, PDF (155/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
T4CNT
00H
Back-to-Back
mode
MAX
Duty, Period Update
MAX
MAX
00H
Duty1
Period1
00H
Duty2 Duty3
Period2
Period3
Interrupt Timing
Overflow INT.
Overflow INT.
Bottom INT.
Overflow INT.
Figure 11.40 Example of Phase Correction and Frequency correction of PWM
External Sync
If using ESYNC bit of T4PCR1 register, it is possible to synchronize the output of PWM from external signal.
If ESYNC bit sets to ‘1’, the external signal moves to PWM module through the BLNK pin. If BLNK signal is low,
immediately PWM output becomes a reset value, and internal counter becomes reset. If BLNK signal returns to
‘1’, the counter is started again and PWM output is normally generated. (Figure 11.41 referred)
PWM Halt
If using PHLT bit of T4PCR1 register, it is possible to stop PWM operation by the software. During PHLT bit
being ‘1’, PWM output becomes a reset value, and internal counter becomes reset as 0. Without changing PWM
setting, temporarily it is able to stop PWM. In case of T4CNT, when stopping counter, PWM output pin remains
before states. But if PHLT bit sets to ‘1’, PWM output pin has reset value.
T4PCR1 = 40H (EYNC=1)
T4PPRH = 00H
T4PPRL = 2AH
T4ADRH = 00H
T4ADRL = 12H
Source Clock
(fx)
BLNK “0”
PWM STOP
BLNK “1”
PWM Restart
T4
00 01 02 12 13 14 2A 00 01 02 12 13 14 00 00 00 00 01 02 03 12 13 14 2A 00 01 02
P02/PWM
POLAA = 1
BLNK
ESYNC = 1
Counter
Stop
Figure 11.41 Example of PWM External Synchronization with BLNK Input
PS029902-0212
PRELIMINARY
152