Z51F3220FNX Datasheet, PDF (7/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
List of Figures
Figure 1.4 StandAlone Gang8 (for Mass Production) ............................................................................... 15
Figure 2.1 Block Diagram .......................................................................................................................... 16
Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment .............................................................................. 17
Figure 3.2 Z51F3220 32SOP Pin Assignment .......................................................................................... 18
Figure 4.1 44-Pin MQFP Package............................................................................................................. 19
Figure 4.2 32-Pin SOP Package................................................................................................................ 20
Figure 6.1 General Purpose I/O Port ......................................................................................................... 26
Figure 6.2 External Interrupt I/O Port ........................................................................................................ 27
Figure 7.1 AC Timing ................................................................................................................................. 35
Figure 7.2 SPI0/1/2 Timing ........................................................................................................................ 36
Figure 7.3 Waveform for UART0/1 Timing Characteristics ....................................................................... 37
Figure 7.4 Timing Waveform for the UART0/1 Module ............................................................................. 37
Figure 7.5 I2C0/1 Timing ........................................................................................................................... 38
Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt ...................................................... 39
Figure 7.7 Stop Mode Release Timing when Initiated by RESETB .......................................................... 39
Figure 7.8 Crystal/Ceramic Oscillator ........................................................................................................ 41
Figure 7.9 External Clock........................................................................................................................... 41
Figure 7.10 Crystal Oscillator .................................................................................................................... 42
Figure 7.11 External Clock......................................................................................................................... 42
Figure 7.12 Clock Timing Measurement at XIN ........................................................................................ 43
Figure 7.13 Clock Timing Measurement at SXIN ...................................................................................... 43
Figure 7.14 Operating Voltage Range....................................................................................................... 44
Figure 7.15 Recommended Circuit and Layout......................................................................................... 45
Figure 7.16 RUN (IDD1 ) Current .............................................................................................................. 46
Figure 7.17 IDLE (IDD2) Current ............................................................................................................... 46
Figure 7.18 SUB RUN (IDD3) Current....................................................................................................... 47
Figure 7.19 SUB IDLE (IDD4) Current ...................................................................................................... 47
Figure 7.20 STOP (IDD5) Current ............................................................................................................. 48
Figure 8.1 Program Memory ...................................................................................................................... 50
Figure 8.2 Data Memory Map .................................................................................................................... 51
Figure 8.3 Lower 128 Bytes RAM.............................................................................................................. 52
Figure 8.4 XDATA Memory Area ............................................................................................................... 53
Figure 10.1 External Interrupt Description................................................................................................. 83
Figure 10.2 Block Diagram of Interrupt...................................................................................................... 84
Figure 10.3 Interrupt Vector Address Table .............................................................................................. 86
Figure 10.4 Effective Timing of Interrupt Enable Register ....................................................................... 87
Figure 10.5 Effective Timing of Interrupt Flag Register............................................................................. 87
Figure 10.6 Effective Timing of Interrupt ................................................................................................... 88
Figure 10.7 Interrupt Response Timing Diagram ...................................................................................... 89
Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP .................. 89
Figure 10.9 Saving/Restore Process Diagram and Sample Source ......................................................... 89
Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction............................... 90
Figure 11.1 Clock Generator Block Diagram............................................................................................. 99
Figure 11.2 Basic Interval Timer Block Diagram ..................................................................................... 102
PS029902-0212
PRELIMINARY
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