Z51F3220FNX Datasheet, PDF (71/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
P15DB (P1/P5 Debounce Enable Register) : DFH
7
6
5
4
–
–
P54DB
P52DB
–
–
R/W
R/W
3
P17DB
R/W
2
P16DB
R/W
1
P12DB
R/W
0
P11DB
R/W
Initial value : 00H
P54DB
P52DB
P17DB
P16DB
P12DB
P11DB
Configure Debounce of P54 Port
0
Disable
1
Enable
Configure Debounce of P52 Port
0
Disable
1
Enable
Configure Debounce of P17 Port
0
Disable
1
Enable
Configure Debounce of P16 Port
0
Disable
1
Enable
Configure Debounce of P12 Port
0
Disable
1
Enable
Configure Debounce of P11 Port
0
Disable
1
Enable
NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid
edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.
4. Refer to the port 0 debounce enable register (P0DB) for the debounce clock of port 1 and port 5.
PS029902-0212
PRELIMINARY
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