Z51F3220FNX Datasheet, PDF (189/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.12.3 USI0 UART Block Diagram
Master
SCK0
ACK
Control
2
USI0MS[1:0]
To interrupt
block
SCLK
(fx: System clock)
USI0BD
Baud Rate Generator
DBLS0
WAKEIE0
RXCIE0
At Stop mode
Clock
Sync Logic
WAKE0
Low level
RXC0
detector
I
RXD0
M
U
X
Rx
Control
LOOPS 0 ^RXE0
Data
Recovery
N
Clock
T
Recovery
E
USI0S[2:0]
R
N
3
A
M
L
Receive Shift Register
(RXSR)
U
X
B
U
DOR0/PE 0/FE0
Checker
2
USI0 DR[0], USI0RX8 [0], (Rx) USI0MS[1:0 ]
S
L
USI0SB
USI0 DR[1], USI0RX8 [1], (Rx)
I
N
TXE0
Stop bit
Generator
USI0P[1:0]
2
USI0S[2:0]
USI0MS[1:0]
E
3
2
TXD0
Tx
Control
Parity
Generator
M
Transmit Shift Register
(TXSR)
U
X
Clear
INT_ACK
TXC0
Empty signal
DRE0
USI0DR, USI0 TX8 , (Tx)
TXCIE0
DRIE0
To interrupt
block
Figure 11.57 USI0 UART Block Diagram
PS029902-0212
PRELIMINARY
187