Z51F3220FNX Datasheet, PDF (69/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
P0DB (P0 Debounce Enable Register) : DEH
7
6
5
4
DBCLK1
DBCLK0
P07DB
P06DB
R/W
R/W
R/W
R/W
3
P05DB
R/W
2
P04DB
R/W
1
P03DB
R/W
0
P02DB
R/W
Initial value : 00H
DBCLK[1:0]
P07DB
P06DB
P05DB
P04DB
P03DB
P02DB
Configure Debounce Clock of Port
DBCLK1 DBCLK0 Description
0
0
fx/1
0
1
fx/4
1
0
fx/4096
1
1
Reserved
Configure Debounce of P07 Port
0
Disable
1
Enable
Configure Debounce of P06 Port
0
Disable
1
Enable
Configure Debounce of P05 Port
0
Disable
1
Enable
Configure Debounce of P04 Port
0
Disable
1
Enable
Configure Debounce of P03Port
0
Disable
1
Enable
Configure Debounce of P02 Port
0
Disable
1
Enable
NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the
signal is eliminated as noise.
2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid
edge.
3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.
PS029902-0212
PRELIMINARY
66