Z51F3220FNX Datasheet, PDF (258/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
USI1CR4 (USI1 Control Register 4: For I2C mode) : ECH
7
6
5
4
3
IIC1IFR
–
TXDLYENB1 IIC1IE
ACK1EN
R
–
R/W
R/W
R/W
2
IMASTER1
R
1
0
STOPC1 STARTC1
R/W
R/W
Initial value : 00H
IIC1IFR
TXDLYENB1
IIC1IE
ACK1EN
IMASTER1
STOPC1
STARTC1
This is an interrupt flag bit for I2C mode. When an interrupt occurs, this
bit becomes ‘1’. This bit is cleared when write any values in th USI1ST2.
0
I2C interrupt no generation
1
I2C interrupt generation
USI1SDHR register control bit
0
Enable USI1SDHR register
1
Disable USI1SDHR register
Interrupt Enable bit for I2C mode
0
Interrupt from I2C is inhibited (use polling)
1
Enable interrupt for I2C
Controls ACK signal Generation at ninth SCL1 period.
0
No ACK signal is generated (SDA1 =1)
1
ACK signal is generated (SDA1 =0)
NOTES) ACK signal is output (SDA1 =0) for the following 3 cases.
1. When received address packet equals to USI1SLA bits in USI1SAR.
2. When received address packet equals to value 0x00 with GCALL1
enabled.
3. When I2C operates as a receiver (master or slave)
Represent operating mode of I2C
0
I2C is in slave mode
1
I2C is in master mode
When I2C is master, STOP condition generation
0
No effect
1
STOP condition is to be generated
When I2C is master, START condition generation
0
No effect
1
START or repeated START condition is to be generated
PS029902-0212
PRELIMINARY
256