Z51F3220FNX Datasheet, PDF (283/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
13.6 External RESETB Input
The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over
within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After
reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET
becomes ‘1’. The Reset process step needs 5 oscillator clocks. And the program execution starts at the vector
address stored at address 0000H.
OSC
RESETB
Internal
RESETB
ADDRESS
BUS
CORE
BUS
TST = 16.4ms
1 234 5
Release
Release
?
?
00
01 02 ?
Stabilization Time
?
?
? 02 ? ? ?
RESET Process
Step
Main Program
Figure 13.7 Timing Diagram after RESET
VDD
PRESCALER COUNT START
OSC START TIMING
Figure 13.8 Oscillator generating waveform example
NOTE) As shown Figure 13.8, the stable generating time is not included in the start-up time.
The RESETB pin has a Pull-up register by H/W.
PS029902-0212
PRELIMINARY
281