Z51F3220FNX Datasheet, PDF (87/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
10.3 Block Diagram
EIPOL1
IE
EINT10
EIFLAG 1 .1
FLAG 10
EINT11
EIFLAG 1 .2
FLAG 11
USI1 I2C
USI1 Rx
I2C1IFR
USI1 Tx
EIPOL0H/L
EINT0
EINT1
EINT2
EINT3
EINT4
EINT5
EINT6
EINT7
FLAG 0
FLAG 1
FLAG 2
FLAG 3
FLAG 4
FLAG 5
FLAG6
FLAG7
EIFLAG 0 .0
EIFLAG 0 .1
EIFLAG 0 .2
EIFLAG 0 .3
EIFLAG 0 .4
EIFLAG 0 .5
EIFLAG 0 .6
EIFLAG 0 .7
EIPOL1
IE1
EINT8
EIFLAG 1.0
FLAG 8
USI0 I2C
I2C0IFR
USI0 Rx
USI0 Tx
EINT12
EIFLAG 1.3
FLAG 12
EIPOL1
Timer 0 overflow
Timer 0
Timer 1
Timer 2
Timer 3
IE2
T0OVIFR
T0IFR
T 1IFR
T2IFR
T3IFR
IP
IP1
0000
1111
2222
3333
4
444
5
555
Priority High
6
666
7
777
8
888
9
999
10
10 _{10 10}
11 _{11 11 11}
12 _{12 12 12}
13 _{13 13 13}
14 _{14 14 14}
15 _{15 15 15}
16 _{16 16 16}
17 _{17 17 17}
Level 0
Level 1
Level 2
Level 3
Release
Stop/Sleep
EA
Timer 4
ADC
SPI2
WT
WDT
BIT
IE3
ADCIFR
SPIIFR
WTIFR
WDTIFR
BITIFR
18 _{18 18 18}
19 _{19 19 19}
20
20 _{20 20}
21
21 _{21 21}
22
22 _{22 22}
23
23 _{23 23}
Priority Low
Figure 10.2 Block Diagram of Interrupt
NOTES) 1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled
without reference to the priority level.
2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register.
PS029902-0212
PRELIMINARY
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