Z51F3220FNX Datasheet, PDF (127/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.6.4 16-Bit PPG Mode
The timer 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs
up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P1FSRL[5:4] to
‘11’ . The period of the PWM output is determined by the T1ADRH/T1ADRL. And the duty of the PWM output is
determined by the T1BDRH/T1BDRL.
T1 CRH
T1EN
1
–
T1MS1 T1MS0
–
–
1
1
–
T1CRL T1CK2 T1CK1 T1CK0 T1IFR
–
X
X
X
X
–
–
–
T1CC
ADDRESS:BBH
INITIAL VALUE : 0000 _0000 B
–
–
X
T1POL T1ECE T1CNTR
X
X
X
ADDRESS:BAH
INITIAL VALUE : 0000 _0000 B
16-bit A Data Register
T1ADRH/T1ADRL
T1ECE
T1 CK[2:0]
3
Reload
Buffer Register A
A Match
T1CC
T1EN
INT_ACK
Clear
EC1
Edge
Detector
P
fx/1
T1 EN
A Match
T1IFR
To interrupt
block
r fx/2
Comparator
e
fx/4
M
fx
s
c
fx/8
U
X
16- bit Counter R
T1CNTH/T1 CNTL
Clear
A Match
T1 CC
T1 EN
a fx/64
l _fx/512
e
r ^fx/2048
B Match
Comparator
Pulse
Generator
2
T1O/
PWM1O
Buffer Register B
T1MS[1 :0] T1POL
Reload
A Match
T1CC
T1EN
16-bit B Data Register
T1 BDRH/T1 BDRL
NOTE) The T1EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode.
Figure 11.19 16-Bit PPG Mode for Timer 1
PS029902-0212
PRELIMINARY
124