Z51F3220FNX Datasheet, PDF (146/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.8.3 16-Bit Timer/Counter 3 Mode
The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31.
The 16-bit timer have counter and data register. The counter register is increased by internal or external clock
input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates
(T3CK[2:0]).
A 16-bit timer/counter register T3CNT, T4CNT are incremented from 0000H to FFFFH until it matches T3DR,
T4DR and then cleared to 0000H. The match signal output generates the Timer 3 Interrupt (No timer 4 interrupt).
The clock source is selected from T3CK[2:0] and 16BIT bit must be set to ‘1’. Timer 3 is LSB 8-bit, the timer 4 is
MSB 8-bit.
The external clock (EC3) counts up the timer at the rising edge. f the EC3 is selected as a clock source by
T3CK[2:0], EC3 port should be set to the input port by P00IO bit.
EC3
fx
T3 CR
T4 CR
T3EN
–
T3MS T3CK2 T3CK1 T3CK0 T3CN T3 ST
1
–
0
X
X
X
X
X
16BIT
1
T4MS
0
T4CN
X
T4ST
X
T4CK3 T4CK2 T4CK1 T4 CK0
1
1
1
1
ADDRESS:1000 H (ESFR)
INITIAL VALUE : 0000 _0000B
ADDRESS:1002 H (ESFR)
INITIAL VALUE : 0000 _0000B
P
fx/2
r
fx/4
e
fx/8
M
s
U
c
fx/32
X
a fx/128
l _fx/512
e
r ^fx/2048
T3CN
3
T3CK[2:0]
T3ST
16-bit Timer 3 Counter
T4CNT/T3CNT (16Bit)
MSB
LSB
Clear
Match
Comparator
T4DR/T3DR (16Bit)
MSB
LSB
16-bit Timer 3 Data Register
INT_ACK
Clear
T3IFR
To interrupt
block
T3 O
NOTE) The T4CR.7 bit (16BIT) should be set to ‘1’ and the T4CK[3:0] should be set to “1111b”.
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
PS029902-0212
PRELIMINARY
143