Z51F3220FNX Datasheet, PDF (136/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.7.3 16-Bit Capture Mode
The timer 2 capture mode is set by T2MS[1:0] as ‘01’. The clock source can use the internal clock. Basically, it
has the same function as the 16-bit timer/counter mode and the interrupt occurs when T2CNTH/T2CNTL is equal
to T2ADRH/T2ADRL. T2CNTH/T2CNTL values are automatically cleared by match signal and it can be also
cleared by software (T2CC).
This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the
maximum period of timer.
The capture result is loaded into T2BDRH/T2BDRL. In the timer 2 capture mode, timer 2 output(T2O) waveform
is not available.
According to EIPOL1 registers setting, the external interrupt EINT12 function is chosen. Of cource, the EINT12
pin must be set to an input port.
T2CRH T2EN
–
T2MS1 T2MS0
–
–
–
T2CC
ADDRESS:C3H
INITIAL VALUE : 0000 _0000B
1
–
0
1
–
–
–
X
T2CRL T2 CK2 T2CK1 T2CK0 T2IFR
–
T2POL
– T2CNTR ^ADDRESS:C2H
X
X
X
X
–
X
–
INITIAL VALUE : 0000 _0000B
X
T2CK[2:0]
3
16 -bit A Data Register
T2ADRH/T2ADRL
Reload
Buffer Register A
T1 A Match
P
fx/1
r fx/2
e
fx/4
M
s
U
fx
c
fx/8
X
a fx/32
l _fx/128
e
r ^fx/512
T2EN
Clear
A Match
Comparator
16 -bit Counter _R
T2CNTH/T2CNTL
Clear
A Match
T2CC
T2EN
INT_ACK
Clear
T2IFR
To interrupt
block
A Match
T2CC
T2EN
EINT12
EIPOL 1[7:6 ]
2
T2CNTR
2
T2MS[1 :0]
16 -bit B Data Register
T2BDRH/T2BDRL
INT_ACK
Clear
FLAG 12
(EIFLAG1.3)
To interrupt
block
Figure 11.24 16-Bit Capture Mode for Timer 2
PS029902-0212
PRELIMINARY
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