Z51F3220FNX Datasheet, PDF (112/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.4.3 Register Map
Table 11-4 Watch Timer Register Map
Name
Address
Dir
WTCNT
89H
R
WTDR
89H
W
WTCR
96H
R/W
Default
00H
7FH
00H
Description
Watch Timer Counter Register
Watch Timer Data Register
Watch Timer Control Register
11.4.4 Watch Timer Register Description
The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR),
and watch timer control register (WTCR). As WTCR is 6-bit writable/ readable register, WTCR can control the
clock source (WTCK[1:0]), interrupt interval (WTIN[1:0]), and function enable/disable (WTEN). Also there is WT
interrupt flag bit (WTIFR).
11.4.5 Register Description for Watch Timer
WTCNT (Watch Timer Counter Register: Read Case) : 89H
7
6
5
4
3
–
WTCNT 6 WTCNT 5 WTCNT 4 WTCNT 3
–
R
R
R
R
WTCNT[6:0] WT Counter
2
WTCNT 2
R
1
0
WTCNT 1 WTCNT0
R
R
Initial value : 00H
WTDR (Watch Timer Data Register: Write Case) : 89H
7
6
5
4
3
WTCL
WTDR 6
WTDR 5
WTDR 4
WTDR 3
R/W
W
W
W
W
2
WTDR 2
W
1
0
WTDR 1
WTDR 0
W
W
Initial value : 7FH
WTCL
WTDR[6:0]
Clear WT Counter
0
Free Run
1
Clear WT Counter (auto clear after 1 Cycle)
Set WT period
WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1))
NOTE) Do not write “0” in the WTDR register.
PS029902-0212
PRELIMINARY
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