Z51F3220FNX Datasheet, PDF (123/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.6 Timer 1
11.6.1.1 Overview
The 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and
timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).
It has four operating modes:
- 16-bit timer/counter mode
- 16-bit capture mode
- 16-bit PPG output mode (one-shot mode)
- 16-bit PPG output mode (repeat mode)
The timer/counter 1 can be clocked by an internal or an external clock source (EC1). The clock source is
selected by clock selection logic which is controlled by the clock selection bits (T1CK[2:0]).
- TIMER 1 clock source: fX/1, 2, 4, 8, 64, 512, 2048 and EC1
In the capture mode, by EINT11, the data is captured into input capture data register (T1BDRH/T1BDRL). Timer
1 outputs the comparision result between counter and data register through T1O port in timer/counter mode. Also
Ttimer 1 outputs PWM wave form through PWM1O port in the PPG mode.
T1EN
1
1
1
1
Table 11-7 Timer 1 Operating Modes
P1FSRL[5:4]
11
00
11
11
T1MS[1:0]
00
01
10
11
T1CK[2:0]
XXX
XXX
XXX
XXX
Timer 1
16 Bit Timer/Counter Mode
16 Bit Capture Mode
16 Bit PPG Mode
(one-shot mode)
16 Bit PPG Mode
(repeat mode)
11.6.2 16-Bit Timer/Counter Mode
The 16-bit timer/counter mode is selected by control register as shown in Figure 11.14.
The 16-bit timer have counter and data register. The counter register is increased by internal or external clock
input. Timer 1 can use the input clock with one of 1, 2, 4, 8, 64, 512 and 2048 prescaler division rates (T1CK[2:0]).
When the value of T1CNTH, T1CNTL and the value of T1ADRH, T1ADRL are identical in Timer 1 respectively, a
match signal is generated and the interrupt of Timer 1 occurs. The T1CNTH, T1CNTL value is automatically
cleared by match signal. It can be also cleared by software (T1CC).
The external clock (EC1) counts up the timer at the rising edge. If the EC1 is selected as a clock source by
T1CK[2:0], EC1 port should be set to the input port by P13IO bit.
PS029902-0212
PRELIMINARY
120