Z51F3220FNX Datasheet, PDF (138/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.7.4 16-Bit PPG Mode
The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin
outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set P1FSRL[3:2]
to ‘11’ . The period of the PWM output is determined by the T2ADRH/T2ADRL. And the duty of the PWM output
is determined by the T2BDRH/T2BDRL.
T2CRH T2 EN
–
T2MS1 T2MS0
–
–
–
T2CC
ADDRESS:C3H
INITIAL VALUE: 0000_0000 B
1
–
1
1
–
–
–
X
T2 CRL
T2CK2 T2 CK1 T2CK0
X
X
X
T2IFR
X
–
T2POL
–
X
– T2CNTR ^ADDRESS:C2H
INITIAL VALUE: 0000_0000 B
–
X
T2CK[2 :0]
3
T1 A Match
P
fx/1
r
fx/2
e
fx/4
M
fx
s
c
fx/8
U
X
a fx/32
l _fx/128
e
r ^fx/512
T2EN
16 -bit A Data Register
T2ADRH/T2ADRL
Reload
Buffer Register A
A Match
T2CC
T2EN
INT_ACK
Clear
A Match
Comparator
16 -bit Counter _R
T2CNTH/T2CNTL
Clear
T2 IFR
To interrupt
block
A Match
T2CC
T2EN
B Match
Pulse
Generator
Comparator
Buffer Register B
2
T2MS[1:0 ] T2POL
T2O /
PWM2 O
Reload
A Match
T2CC
T2EN
16-bit B Data Register
T2BDRH/T2BDRL
NOTE) The T2EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode.
Figure 11.27 16-Bit PPG Mode for Timer 2
PS029902-0212
PRELIMINARY
135