Z51F3220FNX Datasheet, PDF (233/312 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F3220
Product Specification
11.13.10.5 USI1 Asynchronous Data Reception
To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery
logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial
frame on the RXD1 pin.
The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD1 pin.
The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16
times of the baud-rate in normal mode and 8 times the aud-rate for double speed mode (DBLS1=1). The
horizontal arrows show the synchronization variation due to the asynchronous sampling process. Note that larger
time variation is shown when using the double speed mode.
RXD1
IDLE
START
BIT0
Sample
(DBLS1 = 0)
Sample
(DBLS1 = 1)
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
0
1
2
3
4
5
6
7
8
1
2
Figure 11.82 Asynchronous Start Bit Sampling (USI1)
When the receiver is enabled (RXE1=1), the clock recovery logic tries to find a high-to-low transition on the
RXD1 line, the start bit condition. After detecting high to low transition on RXD1 line, the clock recovery logic
uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. If more than 2 samples have
logical low level, it is considered that a valid start bit is detected and the internally generated clock is
synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is
repeated for each start bit.
As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data
recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for
each incoming bits for normal mode and 8 times for double speed mode, and uses sample 8, 9 and 10 to decide
data value. If more than 2 samples have low levels, the received bit is considered to a logic ‘0’ and if more than 2
samples have high levels, the received bit is considered to a logic ‘1’. The data recovery process is then repeated
until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift
register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first
stop bit, the Receiver is in idle state and waiting to find start bit.
RXD1
Sample
(DBLS1 = 0)
Sample
(DBLS1 = 1)
BIT n
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
1
2
3
4
5
6
7
8
1
Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1)
PS029902-0212
PRELIMINARY
231