W83L517D Datasheet, PDF (97/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read
cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
76 5 4 3 2 1 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
6.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
7
6
5
4
Data Port (R/W)
PD7 PD6 PD5 PD4
Status Buffer (Read) BUSY# ACK# PE SLCT
Control Swapper (Read)
1
Control Latch (Write)
1
1
1 IRQEN
1 DIR IRQ
EPP Address Port R/W) PD7
PD6 PD5 PD4
EPP Data Port 0 (R/W) PD7 PD6 PD5 PD4
EPP Data Port 1 (R/W) PD7 PD6 PD5 PD4
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
PD7
PD7
PD6 PD5 PD4
PD6 PD5 PD4
3
PD3
ERROF#
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
2
PD2
1
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
1
PD1
1
AUTOFD#
AUTOFD#
PD1
PD1
PD1
PD1
PD1
0
PD0
TMOUT
STROBE#
STROBE#
PD0
PD0
PD0
PD0
PD0
90
Publication Release Date: Apr. 2000
Revision 0.60