W83L517D Datasheet, PDF (92/138 Pages) Winbond – LPC SUPER I/O

W83L517D
5.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)
Version 0.6
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM_CR AM_FMT IRX_MSL IRSL0D RXINV TXINV
-
-
-
Default Value
0
0
0
0
0
0
0
0
Bit 7:
AM_FMT - Automatic Format
A write to 1 will enable automatic format IR front-end module. These bits will affect the
output of IR_SL2~0 which is referred by IR front-end module selection (Set7.Reg4~6)
Bit 6:
IRX_MSL - IR Receiver Module Select
Select the receiver input path from the IR front end module if IR module has a separated
high speed and low speed receiver path. If the IR module has only one receiving path,
then this bit should be set to 0.
IRX_MSL
Receiver Pin selected
0
IRRX (Low/High Speed)
1
IRRXH (High Speed)
Bit 5:
IRSL0D - Direction of IRSL0 Pin
Select function for IRRXH or IRSL0 because they share common pin and have different
input/output direction.
IRSL0_D
Function
0
IRRXH (I/P)
1
IRSL0 (O/P)
Table: IR receiver input pin selection
IRSL0D
IRX_MSL
AUX_RX
High Speed IR
Selected IR Pin
0
0
0
X
IRRX
0
0
1
X
IRRXH
0
1
X
0
IRRX
0
1
X
1
IRRXH
1
0
0
X
IRRX
1
0
1
X
Reserved
1
1
X
0
IRRX
1
1
X
1
Reserved
Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M
bps) and FIR (4M bps), (3) IRRX is the input of the low speed or high speed IR receiver, IRRXH is the
input of the high speed IR receiver.
Bit 4:
RXINV - Receiving Signal Invert
A write to 1 will Invert the receiving signal.
85
Publication Release Date: Apr. 2000
Revision 0.60