W83L517D Datasheet, PDF (61/138 Pages) Winbond – LPC SUPER I/O

Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
W83L517D
Version 0.6
Bit 5, 4: These two bits are always logical 0.
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1
when a time-out interrupt is pending.
Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to logical 0.
TABLE: INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt Interrupt Type
3 2 1 0 priority
Interrupt Source
Clear Interrupt
0 001-
-
No Interrupt pending
-
0 1 1 0 First
IR Receive Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0 1 0 0 Second RBR Data Ready
1. RBR data ready
2. FIFO interrupt
reached
active
level
1. Read RBR
2. Read RBR until FIFO
data under active level
1 1 0 0 Second FIFO Data Time-out Data present in RX FIFO for 4 Read RBR
characters period of time since last
access of RX FIFO.
0 0 1 0 Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR:
Bit 7:
TMR_I - Timer Interrupt.
Set to 1 when timer counts to logical 0. This bit is valid when: (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is set to
1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1.
Bit 6:
MIR, FIR modes:
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame Status
FIFO time-out occurs. Cleared to 0 when Frame Status FIFO is below the threshold level.
Advanced SIR/ASK-IR, Remote IR modes: Not used.
Bit 5:
TXTH_I - Transmitter Threshold Interrupt.
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Publication Release Date: Apr. 2000
Revision 0.60