W83L517D Datasheet, PDF (35/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
3.2 Register Descriptions
There are several status, data, and control registers in W83L517D. These registers are defined below:
ADDRESS
OFFSET
base address + 0
base address + 1
base address + 2
base address + 3
base address + 4
base address + 5
base address + 7
REGISTER
READ
WRITE
SA REGISTER
SB REGISTER
DO REGISTER
TD REGISTER
TD REGISTER
MS REGISTER
DR REGISTER
DT (FIFO) REGISTER
DT (FIFO) REGISTER
DI REGISTER
CC REGISTER
3.2.1 Status Register A (SA Register) (Read base address + 0)
This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode,
the bit definitions for this register are as follows:
765 43 ²¹ 0
DIR
WP
INDEX
HEAD
TRAK0
STEP
DRV2
INIT PENDING
INIT PENDING (Bit 7):
This bit indicates the value of the floppy disk interrupt output.
DRV2# (Bit 6):
0
A second drive has been installed
1
A second drive has not been installed
STEP (Bit 5):
This bit indicates the complement of STEP# output.
TRAK0# (Bit 4):
This bit indicates the value of TRAK0# input.
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Publication Release Date: Apr. 2000
Revision 0.60