W83L517D Datasheet, PDF (41/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
3.2.6 Data Rate Register (DR Register) (Write base address + 4)
The Data Rate Register is used to set the transfer rate and write pre-compensation. The data rate of the
FDC is programmed via the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by
the DR REGISTER. The real data rate is determined by the most recent write to either of the DR
REGISTER or CC REGISTER.
7 6 5 4 3 21 0
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0 FDC in normal mode
1 FDC in power-down mode
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the pre-
compensation values for the combination of these bits.
PRECOMP
210
000
001
010
011
100
101
110
111
PRECOMPENSATION DELAY
250K - 1 Mbps
2 Mbps Tape drive
Default Delays
41.67 nS
Default Delays
20.8 nS
83.34 nS
41.17 nS
125.00 nS
62.5nS
166.67 nS
83.3 nS
208.33 nS
250.00 nS
104.2 nS
125.00 nS
0.00 nS (disabled)
0.00 nS (disabled)
34
Publication Release Date: Apr. 2000
Revision 0.60