W83L517D Datasheet, PDF (62/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level. Cleared
to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level.
Bit 4:
MIR, FIR, Remote IR Modes:
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which might
be a transmitter TC or a Receiver TC. Cleared to 0 when this register is read.
Bit 3:
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when Handshake
Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-IR, MIR, FIR,
and Remote Control IR, this bit defaults to be inactive unless IR Handshake Status Enable
(IRHS_EN) is set to 1.
Bit 2:
Advanced SIR/ASK-IR modes:
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error is detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
MIR, FIR modes:
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is defined in
the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been detected
during receiving valid data. Cleared to 0 when this register is read.
Remote Controller Mode: Not used.
Bit 1:
TXEMP_I - Transmitter Empty.
Set to 1 when transmitter (or, say, FIFO + Transmitter) is empty. Cleared to 0 when this
register is read.
Bit 0:
RXTH_I – Receiver Threshold Interrupt.
Set to 1 when (1) the Receiver Buffer Register (RBR) is equal or larger than the threshold
level; or (2) RBR time-out occurs if the receiver buffer register has valid data and is below the
threshold level. Cleared to 0 when RBR is less than threshold level after reading RBR.
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Publication Release Date: Apr. 2000
Revision 0.60