W83L517D Datasheet, PDF (137/138 Pages) Winbond – LPC SUPER I/O

13 Recommended Circuit
FLASH ROM
U1
XA[0..18]
MEMW#
MEMR#
ROMCS#
XA18
XA17
XA16
1
30
2
NC/A18
A17
XA15
XA14
XA13
XA12
3
29
28
4
A16
A15
A14
A13
XA11
XA10
XA9
XA8
25
23
26
27
A12
A11
A10
A9
XA7
XA6
XA5
XA4
5
6
7
8
A8
A7
A6
A5
XA3
XA2
XA1
XA0
9
10
11
12
A4
A3
A2
A1
A0
31
24
WE#
22
OE#
CE#
DQ0
DQ1
13
14
15
DQ2
DQ3
DQ4
DQ5
17
18
19
20
DQ6
DQ7
21
VCC ³²
16
GND
W29C020/40
Note6:
(Before updating the code of flash ROM,CR
registers of W83L517D and chipset must be
setted)
5VCC
3VCC
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
5VCC
O.1U
C1
XD[0..7]
XA6
XA7
XA8
XA9
XA10
XA11
XA12
XA13
XA14
GND
XA15
XA16
XA17
XA18
RP1
XA0
2
1
XA1
3
XA2
4
XA3
5
XA4
6
XA5
7
XA6
8
XA7
9
XA8 10
5VCC
RP2
LAD0 2
1
LAD1 3
LAD2 4
LAD3 5
LFRAME# 6
SERIRQ 7
PDCTL# 8
9
10
5VCC
HEAD#
RDATA#
WP#
TRACK0#
WE#
WD#
STEP#
DIR#
MOA#
DSKCHG#
8.2K
8.2K
RP3
XA9
2
1
Note8:
XA10 3
XA11 4
XA12 5
XA13 6
XA14 7
The resistor of SERIRQ is option if Host
connected.
XA15 8
XA16 9
XA17 10
5VCC
XD3
XD4
XD6
XD7
MEMR#
MEMW#
ROMCS#
XA0
XA1
XA2
XA3
XA4
XA5
76
77
XA6/GP43
78
79
80
81
XA7/GP44
XA8/GP45
XA9/GP46
XA10/GP47
82
83
84
85
XA11/GP50
XA12/GP51
XA13/GP52
XA14/GP53
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
XA15/GP54
XA16/GP55
XA17/GP56
XA18/GP57
VCC
HEAD#
RDATA#
WP#
TRACK0#
WE#
WD#
STEP#
DIR#
MOA#
DSKCHG#
8.2K
R1
5VCC
IRQ1IN
RP4
XA18 2
1
XD0
3
8.2K
XD1
4
XD2
5
R2
XD3
6
IRQ12IN
XD4
7
XD5
8
XD6
9
8.2K
XD7 10
8.2K
DSA#
Note1:
INDEX#
DRVDEN0
(P80CS#
(RTCCS#
is decoded 80h and IOW#)
is decoded 70h and 71h)
(CLKIN is 24 or 48MHz)
P80CS#
RTCCS#
CLKIN
PME#
(PDCTL# should connect a
pull-high resistor)
LREST#
PDCTL#
GND
SERIRQ
PCICLK
3VCC or 3VCC(stand by)
R6
4.7K
W83L517D
Version 0.6
XD5
GND
XD2
XD1
XD0
IOW#
IOR#
IRQ12IN
IRQ1IN
MCCS#
KBCS#
3VCC
U3
IRSEL0
50
49
IRTX
IRRX
RIA#
DCDA#
48
47
46
45
SOUTA/PEN48
SINA
DTRA#/PNPCSV#
RTSA#/HEFRAS
44
43
42
41
DSRA#
VCC
CTSA#
STB#
AFD#
ERR#
GND
INIT#
SLIN#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
COM PORT
5VCC
RTSA#
DTRA#
SOUTA
RIA#
CTSA#
DSRA#
SINA
DCDA#
U2
20 _VCC
+12V ¹
16
15
13
19
18
DA1
DA2
DA3
RY1
17
14
12
RY2
RY3
RY4
RY5
5
DY1
DY2
DY3
RA1
6
8
2
3
RA2
RA3
RA4
RA9
4
7
9
11 _GND
-12V ¹⁰
14185
(SOP20)
12VCC
NRTSA
NDTRA
NSOUTA
NRIA
NCTSA
NDSRA
NSINA -12VCC
NDCDA
IRSEL0
IRTX
IRRX
RIA#
DCDA#
SOUTA
SINA
DTRA#
RTSA#
DSRA#
5VCC
CTSA#
STB#
AFD#
ERR#
GND
INIT#
SLIN#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
NRIA
NDTRA
NCTSA
NSOUTA
NRTSA
NSINA
NDSRA
NDCDA
P1
5
9
4
8
3
7
2
6
1
CONNECTOR DB9
FIR/SIR CON.
5VCC/3VCC
IRSEL0
IRRX
IRTX
JP1
1
2
3
4
5
HEADER 5
W83L517D
Note2:
PD0
ACK#
BUSY
PE
Note3:
SLCT
PRT_NFDD#
(PRT_NFDD#
is
used
to
detect
external
FDD)
LFRAME#
LAD3
LAD2
LAD1
3VCC
LAD0
LDRQ#
(LDRQ# is connected to either one LDRQX of chipset)
inbond
Title
W83L517D LPC SUPER I/O
Size Document Number
B L517_1
Date:
Tuesday, June 27, 2000
Sheet 1 of
Rev
0.2
130
Publication Release Date: Apr. 2000
Revision 0.60