W83L517D Datasheet, PDF (4/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
4 UART PORT ......................................................................................................... 40
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A) .................................. 40
4.2 REGISTER ADDRESS .............................................................................................................. 40
4.2.1 UART Control Register (UCR) (Read/Write) ........................................................................ 40
4.2.2 UART Status Register (USR) (Read/Write).......................................................................... 42
4.2.3 Handshake Control Register (HCR) (Read/Write) ................................................................ 44
4.2.4 Handshake Status Register (HSR) (Read/Write).................................................................. 45
4.2.5 UART FIFO Control Register (UFR) (Write only) ................................................................. 46
4.2.6 Interrupt Status Register (ISR) (Read only).......................................................................... 47
4.2.7 Interrupt Control Register (ICR) (Read/Write) ...................................................................... 48
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)..................................................... 48
4.2.9 User-defined Register (UDR) (Read/Write) .......................................................................... 49
5. INFRARED (IR) PORT......................................................................................... 50
5.1 IR REGISTER DESCRIPTION .................................................................................................. 50
5.2 SET0-LEGACY/ADVANCED IR CONTROL AND STATUS REGISTERS .................................. 51
5.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write) ...................... 52
5.2.2 Set0.Reg1 - Interrupt Control Register (ICR)........................................................................ 52
ETMRI - Enable Timer Interrupt .......................................................................................... 52
5.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR) ......................... 53
5.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR): ....................................... 57
5.2.5 Set0.Reg4 - Handshake Control Register (HCR) ................................................................. 58
5.2.6 Set0.Reg5 - IR Status Register (USR)................................................................................. 60
5.2.7 Set0.Reg6 - Reserved ......................................................................................................... 61
5.3 SET1 - LEGACY BAUD RATE DIVISOR REGISTER................................................................. 62
5.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ............................................................. 63
5.3.2 Set1.Reg 2~7 ...................................................................................................................... 63
5.4 SET2 - INTERRUPT STATUS OR IR FIFO CONTROL REGISTER (ISR/UFR)......................... 64
5.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL) ................................................ 64
5.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1) ................................................................ 64
5.4.3 Reg3 - Sets Select Register (SSR)...................................................................................... 65
5.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2) ................................................................ 65
5.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only) ...................................................... 68
5.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only).......................................................... 68
II
Publication Release Date: Apr. 2000
Revision 0.60