W83L517D Datasheet, PDF (84/138 Pages) Winbond – LPC SUPER I/O

5.8.3 Set6.Reg2 - SIR Pulse Width
Reg.
Bit 7
Bit 6
SIR_PW
-
-
Reset Value
0
0
Bit 5
-
0
W83L517D
Version 0.6
Bit 4
S_PW4
0
Bit 3
S_PW3
0
Bit 2
S_PW2
0
Bit 1
S_PW1
0
Bit 0
S_PW0
0
This 5-bit register sets SIR output pulse width.
S_PW4~0
SIR Output Pulse Width
00000
3/16 bit time of IR
01101
1.6 us
Others
1.6 us
5.8.4 Set6.Reg3 - Set Select Register
Select Register Set by writing a set number to this register. Reading this register returns F0H.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 SRR0
Default Value
1
1
1
1
0
0
0
0
5.8.5 Set6.Reg4 - High Speed Infrared Beginning Flag Number (HIR_FNU)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
HIR_FNU M_FG3 M_FG2 M_FG1 M_FG0 F_FL3 F_FL2
Reset Value
0
0
1
0
1
0
Bit 1
F_FL1
1
Bit 0
F_FL0
0
Bit 7~4:
M_FG3~0 - MIR beginning Flag Number
These bits define the number of transmitter Start Flag of MIR. Note that the number of
MIR start flag should be equal or more than two which is defined in IrDA 1.1 physical
layer. The default value is 2.
M_FG3~0
Beginning Flag Number
M_FG3~0
Beginning Flag Number
0000
0001
0010
0011
0100
0101
0110
0111
Reserved
1
2 (Default)
3
4
5
6
8
1000
1001
1010
1011
1100
1101
1110
1111
10
12
16
20
24
28
32
Reserved
77
Publication Release Date: Apr. 2000
Revision 0.60