W83L517D Datasheet, PDF (117/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Bit 1: PRTTRI
Version 0.6
When write to “1”, PRT interface is set to tri-state and reduce the power consumption of chip.
Bit 0: FDCTRI.
When write to “1”,FDC interface is set to tri-state and reduce the power consumption of chip.
CR26 (Default 0s00,000b)
Bit 7: Reserved
Bit 6: HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is RTSA# (pin 42).
HEFRAS Address and Value
= 0 Write 87h to the location 2E twice.
= 1 Write 87h to the location 4Etwice.
Bit 5: LOCKREG
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
Bit 4: Reserved.
Bit 3: DSFDLGRQ
= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
on selecting IRQ
= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
Bit 2: DSPRLGRQ
= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Bit 1: DSUALGRQ
= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ
= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting
IRQ
Bit 0: DSUBLGRQ
= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ
= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ
110
Publication Release Date: Apr. 2000
Revision 0.60