W83L517D Datasheet, PDF (53/138 Pages) Winbond – LPC SUPER I/O

4.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
7 6 54 3 210
W83L517D
Version 0.6
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the
interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO,
the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 4-3 FIFO TRIGGER LEVEL
Bit 7
Bit 6
RX FIFO Interrupt Active Level (Bytes)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR
bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a
logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
other bits of UFR are programmed.
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Publication Release Date: Apr. 2000
Revision 0.60