W83L517D Datasheet, PDF (3/138 Pages) Winbond – LPC SUPER I/O

TABLE OF CONTENTS
W83L517D
Version 0.6
GENERAL DESCRIPTION ......................................................................................... 1
1 PIN DESCRIPTION................................................................................................ 5
1.1 LPC INTERFACE ........................................................................................................................ 5
1.2 FDC INTERFACE........................................................................................................................ 6
1.3 MULTI-MODE PARALLEL PORT ................................................................................................ 7
1.4 SERIAL PORT INTERFACE AND INFRARED PORT................................................................ 11
1.5 KBC AND FLASH ROM INTERFACE ........................................................................................ 13
1.6 POWER PINS ........................................................................................................................... 14
2 LPC (LOW PIN COUNT) INTERFACE ................................................................. 15
3 FDC FUNCTIONAL DESCRIPTION ..................................................................... 16
3.1 W83L517D FDC ........................................................................................................................ 16
3.1.1 AT interface......................................................................................................................... 16
3.1.2 FIFO (Data)......................................................................................................................... 16
3.1.3 Data Separator.................................................................................................................... 17
3.1.4 Write Precompensation ....................................................................................................... 17
3.1.5 Perpendicular Recording Mode............................................................................................ 18
3.1.6 FDC Core............................................................................................................................ 18
3.1.7 FDC Commands.................................................................................................................. 18
3.2 REGISTER DESCRIPTIONS..................................................................................................... 28
3.2.1 Status Register A (SA Register) (Read base address + 0)................................................... 28
3.2.2 Status Register B (SB Register) (Read base address + 1)................................................... 30
3.2.3 Digital Output Register (DO Register) (Write base address + 2)........................................... 32
3.2.4 Tape Drive Register (TD Register) (Read base address + 3) ............................................... 32
3.2.5 Main Status Register (MS Register) (Read base address + 4) ............................................. 33
3.2.6 Data Rate Register (DR Register) (Write base address + 4) ................................................ 34
3.2.7 FIFO Register (R/W base address + 5) ............................................................................... 35
3.2.8 Digital Input Register (DI Register) (Read base address + 7) ............................................... 38
3.2.9 Configuration Control Register (CC Register) (Write base address + 7) ............................... 39
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Publication Release Date: Apr. 2000
Revision 0.60