W83L517D Datasheet, PDF (48/138 Pages) Winbond – LPC SUPER I/O

W83L517D
TABLE 4-1 UART Register Bit Map
Version 0.6
BIT NUMBER
REGISTER ADDRESS BASE
+0
BDLAB = 0
RECEIVER
BUFFER
REGISTER
(READ ONLY)
RBR
+0
BDLAB = 0
TRANSMITTER TBR
BUFFER
REGISTER
(WRITE ONLY)
+1
INTERRUPT ICR
BDLAB = 0
CONTROL
REGISTER
+2
INTERRUPT ISR
STATUS
REGISTER
(READ ONLY)
+2
UART FIFO UFR
CONTROL
REGISTER
(WRITE ONLY)
+3
UART
UCR
CONTROL
REGISTER
+4
HANDSHAKE HCR
CONTROL
REGISTER
+5
UART STATUS USR
REGISTER
+6
HANDSHAKE HSR
STATUS
REGISTER
+7
USER DEFINED UDR
REGISTER
+0
BAUDRATE BLL
BDLAB = 1
DIVISOR
LATCH LOW
+1
BAUDRATE BHL
BDLAB = 1
DIVISOR
LATCH HIGH
0
RX Data
Bit 0
1
RX Data
Bit 1
2
RX Data
Bit 2
3
RX Data
Bit 3
4
RX Data
Bit 4
TX Data
Bit 0
TX Data
Bit 1
TX Data
Bit 2
TX Data
Bit 3
TX Data
Bit 4
RBR Data TBR
Ready
Empty
Interrupt
Interrupt
Enable
Enable
(ERDRI) (ETBREI)
"0"
Interrupt
Pending
if Interrupt
Status
Bit (0)
FIFO
Enable
RCVR
FIFO
Reset
USR
Interrupt
Enable
(EUSRI)
Interrupt
Status
Bit (1)
XMIT
FIFO
Reset
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
DMA
Mode
Select
0
0
Reserved
Data
Length
Select
Bit
(DLS0)
Data
Length
Select
0 Bit
(DLS1)
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
RBR Data Overrun
Ready
Error
(RDR)
(OER)
CTS
Toggling
(TCTS)
Bit 0
DSR
Toggling
(TDSR)
Bit 1
Multiple
Parity
Stop Bits Bit
Enable
Enable
1 _(MSBE)
(PBE)
Loopback
RI
Input
IRQ
Enable
Even
Parity
Enable
(EPE)
Internal
Loopback
Enable
Parity
Error
(PBER)
Bit No
Stop Silent
Bit
Byte
Error
Detected
(NSER)
(SBD)
RI Falling DCD
Edge
Toggling
Clear
to Send
(FERI)
(TDCD)
(CTS)
Bit 2
Bit 3
Bit 4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
5
RX Data
Bit 5
6
RX Data
Bit 6
7
RX Data
Bit 7
TX Data
Bit 5
TX Data
Bit 6
TX Data
Bit 7
0
0
0
0
FIFOs
FIFOs
Enabled
Enabled
**
**
Reversed
RX
RX
Interrupt
Interrupt
Active Level Active Level
(LSB)
(MSB)
Parity
Set
Bit Fixed Silence
Enable
Enable
PBFE)
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
0
0
TBR
Empty
(TBRE)
TSR
Empty
(TSRE)
Data
Ready
(DSR)
Bit 5
Set Ring
Indicator
(RI)
Bit 6
Bit 5
Bit 6
RX FIFO
Error
Indication
(RFEI) **
Data Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 13
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
41
Publication Release Date: Apr. 2000
Revision 0.60