W83L517D Datasheet, PDF (78/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package. These registers are only valid when APM=1 (automatic package mode,
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length if
the transmitted data is larger than the programmed frame length. When these registers are read, they
will return the number of bytes which is not transmitted from a frame length programmed.
5.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RFRLL
Reset Value
RFRLH
Reset Value
bit 7
0
-
-
bit 6
0
-
-
bit 5
bit 4
bit 3
0
0
0
-
bit 12 bit 11
-
0
0
Bit 2
bit 2
0
bit 10
0
Bit 1
bit 1
0
bit 9
0
Bit 0
bit 0
0
bit 8
0
These are combined to be a 13-bit register and up counter. The length of receiver frame will be limited
to the programmed frame length. If the received frame length is larger than the programmed receiver
frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously, the
receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which is
defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data bytes
of a frame from the receiver.
5.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
Address Offset
Register Name
Register Description
0
FCBLL
1
FCBHL
2
FC_MD
3
SSR
4
IRCFG1
5
FS_FO
6
RFRLFL
7
RFRLFH
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
5.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
5.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
FC_MD FC_MD2 FC_MD1 FC_MD0
-
FC_DSW EN_FD EN_BRFC
Bit 0
EN_FC
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Publication Release Date: Apr. 2000
Revision 0.60