W83L517D Datasheet, PDF (47/138 Pages) Winbond – LPC SUPER I/O

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
W83L517D
Version 0.6
4. UART PORT
4.1 Universal Asynchronous Receiver/Transmitter (UART A)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit
format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a
16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to
drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also
include complete modem control capability and a processor interrupt system that may be software trailed
to the computing time required to handle the communication link. The UARTs have a FIFO mode to
reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both
receive and transmit mode.
4.2 Register Address
4.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
7 6 54 3 2 1 0
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary format)
from the divisor latches of the baud rate generator during a read or write operation. When this bit is reset,
the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be
accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected via this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) If EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) If EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
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Publication Release Date: Apr. 2000
Revision 0.60