W83L517D Datasheet, PDF (50/138 Pages) Winbond – LPC SUPER I/O

two cases, this bit will be reset to a logical 0.
W83L517D
Version 0.6
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set to
a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write the
next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will be
reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full word
time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same condition
for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will
clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it will
clear this bit to a logical 0.
Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next
received data before they read by the CPU. In 16550 mode, it indicates the same condition instead of
FIFO full. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the
RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.
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Publication Release Date: Apr. 2000
Revision 0.60