W83L517D Datasheet, PDF (46/138 Pages) Winbond – LPC SUPER I/O

DSKCHG (Bit 7):
This bit indicates the status of DSKCHG# input.
W83L517D
Version 0.6
Bit 6-4: These bits are always logic 1 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO REGISTER bit 3.
NOPREC (Bit 2):
This bit indicates the value of CC REGISTER NOPREC bit.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
3.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as
follows:
7 6 5 ⁴ 3 ²¹ 0
xxxx xx
DRATE0
DRATE1
X: Reserved
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC.
In the PS/2 Model 30 mode, the bit definitions are as follows:
76 5 43 ²¹ 0
XX XX X
DRATE0
DRATE1
NOPREC
X: Reserved
Bit 7-3: Reserved. These bits should be set to 0.
NOPREC (Bit 2):
This bit indicates no pre-compensation. It has no function and can be set by software.
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Publication Release Date: Apr. 2000
Revision 0.60