W83L517D Datasheet, PDF (133/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
to this bit position or by the sleeping/working state machine automatically when the
global standby timer expires.
= 0 the chip is in the sleeping state.
= 1 the chip is in the working state.
Bit 6 - 5: Devices' trap status.
Bit 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
CRF3 (Default 0x00)
Bit 7 ~ 4: Reserved. Return zero when read.
Bit 3 ~ 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device respectively. The device's IRQ status
bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. FIR IRQ status.
CRF4 (Default 0x00)
Bit 7 ~ 4: Reserved. Return zero when read.
Bit 3 ~ 0: These bits indicate the IRQ status of the individual GPIO function or logical device
respectively. The status bit is set by their source function or device and is cleared by
writing a1. Writing a 0 has no effect.
Bit 2: WDTIRQSTS. Watch dog timer IRQ status.
Bit 1~0: Reserved
CRF9 (Default 0x00)
Bit 7 - 3: Reserved. Return zero when read.
Bit 2: PME_EN: Select the power management events to be either an PME or SMI interrupt
for the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1.
= 0 the power management events will generate an SMI event.
= 1 the power management events will generate an PME event.
Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices.
=0 1S
= 1 8 mS.
Bit 0: SMIPME_OE: This is the SMI and PME output enable bit.
= 0 neither SMI nor PME will be generated. Only the IRQ status bit is set.
= 1 an SMI or PME event will be generated.
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Publication Release Date: Apr. 2000
Revision 0.60