W83L517D Datasheet, PDF (104/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
Bit 2: Read/Write
1
Disables DMA and all of the service interrupts.
0
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
The FIFO has at least 1 free byte.
1
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
The FIFO contains at least 1 byte of data.
1
The FIFO is completely empty.
6.3.11 Bit Map of ECP Port Registers
D7
D6
D5
D4
D3
D2
Data
ecpAFifo
Dsr
Dcr
Cfifo
ecpDFifo
Tfifo
CnfgA
CnfgB
Ecr
PD7
Addr/RLE
nBusy
1
0
compress
PD6
nAck
1
0
intrValue
MODE
PD5
PD4
PD3
PD2
Address or RLE field
PError
Select
nFault
1
Directio ackIntEn SelectIn
nInit
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
0
1
0
0
1
1
1
1
nErrIntrEn dmaEn serviceIntr
D1
PD1
1
autofd
0
1
full
D0
PD0
1
strobe
0
1
empty
Note
2
1
1
2
2
2
97
Publication Release Date: Apr. 2000
Revision 0.60