W83L517D Datasheet, PDF (128/138 Pages) Winbond – LPC SUPER I/O

CRF3 (PLED mode register. Default 0x00h)
Bit 7 ~ 3 : Reserved .
Bit 2: select WDTO count mode.
= 0 second
= 1 minute
Bit 1 ~ 0: select PLED mode
= 00b Power LED pin is tri-stated.
= 01b Power LED pin is droved low.
= 10b Power LED pin is a 1Hz toggle pulse with 50 duty cycle.
= 11b Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
W83L517D
Version 0.6
CRF4 (Default 0x00h)
Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to
load the value to Watch Dog Counter and start counting down. Reading this register returns current
value in Watch Dog Counter instead of Watch Dog Timer Time-out value.
Bit 7 - 0:
= 0x00h Time-out Disable
= 0x01h Time-out occurs after 1 second/minute
= 0x02h Time-out occurs after 2 second/minutes
= 0x03h Time-out occurs after 3 second/minutes
................................................
= 0xFFh Time-out occurs after 255 second/minutes
CRF5 (Default 0x00h)
Bit 7 ~ 6 : Reserved .
Bit 5: Force Watch Dog Timer Time-out, Write only*
= 1 Force Watch Dog Timer time-out event; this bit is self-clearing.
Bit 4: Watch Dog Timer Status, R/W
= 1 Watch Dog Timer time-out occurred.
= 0 Watch Dog Timer counting
Bit 3 -0: These bits select IRQ resource for Watch Dog. Setting of 2 selects SMI.
Logical Device 8 ( GPIO Port 2)
CR30 (Default 0x00h)
Bit 7 - 1: Reserved.
Bit 0: = 1 Activate GPIO2
= 0 GPIO2 is inactive.
CR62, CR 63 (Default 0x00h, 0x00h)
These two registers select the GPIO1 base address [0x100:0xFFF] on 1 byte boundary
IO address : CRF1 base address
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Publication Release Date: Apr. 2000
Revision 0.60