W83L517D Datasheet, PDF (76/138 Pages) Winbond – LPC SUPER I/O

W83L517D
5.5.2 Reg1 - Mapped IR Control Register (MP_UCR)
Version 0.6
This register is read only. Reading this register returns IR Control Register value of Set 0.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 SRR0
Default Value
0
0
0
0
0
0
0
0
5.5.3 Reg2 - Mapped IR FIFO Control Register (MP_UFR)
This register is read only. Reading this register returns IR FIFO Control Register (UFR) value of SET 0.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1 SRR0
Default Value
0
0
0
0
0
0
0
0
5.5.4 Reg3 - Sets Select Register (SSR)
Reading this register returns E4H. Writing a value selects a Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2
Default Value
1
1
1
0
0
1
Bit 1
SRR1
0
Bit 0
SRR0
0
5.6 Set4 - TX/RX/Timer counter registers and IR control registers.
Address Offset Register Name
Register Description
0
TMRL
Timer Value Low Byte
1
TMRH
2
IR_MSL
3
SSR
4
TFRLL
Timer Value High Byte
Infrared Mode Select
Sets Select Register
Transmitter Frame Length Low Byte
5
TFRLH
6
RFRLL
7
RFRLH
Transmitter Frame Length High Byte
Receiver Frame Length Low Byte
Receiver Frame Length High Byte
5.6.1 Set4.Reg0, 1 - Timer Value Register (TMRL/TMRH)
This is a 12-bit timer whose resolution is 1ms, that is, the maximum programmable time is 2¹²-1 ms. The
timer is a down-counter and starts counting down when EN_TMR (Enable Timer) of Set4.Reg2 is set to 1.
When the timer counts down to zero and EN_TMR=1, the TMR_I is set to 1 and a new initial value will be
loaded into counter.
69
Publication Release Date: Apr. 2000
Revision 0.60