W83L517D Datasheet, PDF (64/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
Advanced IR:
Bit 7, 6: RXFTL1, 0 – Receiver FIFO Threshold Level
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal to or larger than the defined value shown as follow.
RXFTL1, 0
(Bit 7, 6)
RX FIFO Threshold Level RX FIFO Threshold Level
(FIFO Size: 16-byte)
(FIFO Size: 32-byte)
00
1
1
01
4
4
10
8
16
11
14
26
Note that the FIFO Size is selectable in SET2.Reg4.
Bit 5, 4: TXFTL1, 0 - Transmitter FIFO Threshold Level
TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter
Threshold Level is less than the programmed value shown below.
TXFTL1, 0
(Bit 5, 4)
TX FIFO Threshold Level TX FIFO Threshold Level
(FIFO Size: 16-byte)
(FIFO Size: 32-byte)
00
1
1
01
3
7
10
9
17
11
13
25
Bit 3 ~0: Same as in Legacy IR Mode
5.2.4 Set0.Reg3 - IR Control Register/Set Select Register (UCR/SSR):
These two registers share the same address. In all Register Sets, Set Select Register (SSR) can be
programmed to select a desired Set, but IR Control Register can only be programmed in Set 0 and Set 1.
In other words, writing to Reg3 in Sets other than Set 0 and Set 1 will not affect IR Control Register. The
mapping of entry Set and programming value is shown below.
57
Publication Release Date: Apr. 2000
Revision 0.60