W83L517D Datasheet, PDF (12/138 Pages) Winbond – LPC SUPER I/O

1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t - TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OUT12tp3 - 3.3V TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INcs
- CMOS level Schmitt-trigger input pin
INt
- TTL level input pin
INtd
- TTL level input pin with internal pull down resistor
INts
- TTL level Schmitt-trigger input pin
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
W83L517D
Version 0.6
1.1 LPC Interface
SYMBOL
PIN
CLKIN
6
PME#
7
PCICLK
12
LDRQ#
13
SERIRQ
11
LAD[0:3]
LFRAME#
LRESET#
PDCTL#
14,
16-18
19
8
9
I/O
IN_t
OD₁₂
IN_tsp3
O_12tp3
I/OD12t
I/O_12tp3
FUNCTION
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz
input.
Generated PME event.
PCI clock input.
Encoded DMA Request signal.
Serial IRQ input/Output.; Support both Continuous and Quiet
modes.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
IN_tsp3
IN_tsp3
IN_tsp3
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
Hardware power down input pin for chip power down.
Programmable control by registers.
5
Publication Release Date: Apr. 2000
Revision 0.60