W83L517D Datasheet, PDF (70/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
5.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Set & Register
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Advanced
DIS_BACK=×
Bit 7~5
Bit 0, 5, 7
Bit 2, 3
Mode Legacy
DIS_BACK=0
-
Bit 5, 7
-
Mode
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any
register which is meaningful in legacy SIR/ASK-IR.
5.3.2 Set1.Reg 2~7
These registers are defined the same as Set 0 registers.
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Publication Release Date: Apr. 2000
Revision 0.60