W83L517D Datasheet, PDF (69/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
Bit 3
MIR, FIR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure od PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if used in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Bit 2:
Reserved.
Bit 1:
MIR, FIR Modes:
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends remain in receiver FIFO.
Bit 0:
MIR, FIR, Remote IR Modes:
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
5.3 Set1 - Legacy Baud Rate Divisor Register
Address Offset Register Name
Register Description
0
BLL
1
BHL
2
ISR/UFR
3
UCR/SSR
Baud Rate Divisor Latch (Low Byte)
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
4
HCR
5
USR
6
HSR
7
UDR/ESCR
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
62
Publication Release Date: Apr. 2000
Revision 0.60