W83L517D Datasheet, PDF (52/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
4.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of four input pins for handshake peripherals such as a modem and
records changes on these pins.
7 6 54 321 0
CTS ^{toggling (TCTS)}
DSR toggling (TDSR)
RI falling edge (FERI)
DCD ^{toggling (TDCD)}
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
Bit 7: This bit is the opposite of the DCD input. This bit is equivalent to bit 3 of HCR in loop-back mode.
Bit 6: This bit is the opposite of the RI input. This bit is equivalent to bit 2 of HCR in loop-back mode.
Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loop-back mode.
Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loop-back mode.
Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read by
the CPU.
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
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Publication Release Date: Apr. 2000
Revision 0.60