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W83L517D Datasheet, PDF (6/138 Pages) Winbond – LPC SUPER I/O
W83L517D
Version 0.6
6. PARALLEL PORT .............................................................................................. 86
6.1 PRINTER INTERFACE LOGIC.................................................................................................. 86
6.2 ENHANCED PARALLEL PORT (EPP)....................................................................................... 87
6.2.1 Data Swapper ..................................................................................................................... 87
6.2.2 Printer Status Buffer............................................................................................................ 88
6.2.3 Printer Control Latch and Printer Control Swapper............................................................... 89
6.2.4 EPP Address Port ............................................................................................................... 89
6.2.5 EPP Data Port 0-3............................................................................................................... 90
6.2.6 Bit Map of Parallel Port and EPP Registers ......................................................................... 90
6.2.7 EPP Pin Descriptions .......................................................................................................... 91
6.2.8 EPP Operation .................................................................................................................... 91
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 92
6.3.1 ECP Register and Mode Definitions..................................................................................... 92
6.3.2 Data and ecpAFifo Port ....................................................................................................... 93
6.3.3 Device Status Register (DSR) ............................................................................................. 93
6.3.4 Device Control Register (DCR)............................................................................................ 94
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010......................................................................... 95
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 .............................................................................. 95
6.3.7 tFifo (Test FIFO Mode) Mode = 110 .................................................................................... 95
6.3.8 cnfgA (Configuration Register A) Mode = 111...................................................................... 95
6.3.9 cnfgB (Configuration Register B) Mode = 111...................................................................... 95
6.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 96
6.3.11 Bit Map of ECP Port Registers ........................................................................................ . 97
6.3.12 ECP Pin Descriptions ...................................................................................................... 98
6.3.13 ECP Operation .................................................................................................................. 98
6.3.14 FIFO Operation ................................................................................................................. 99
6.3.15 DMA Transfers .................................................................................................................. 99
6.3.16 Programmed I/O (NON-DMA) Mode .................................................................................. 99
6.4 EXTENSION FDD MODE (EXTFDD)....................................................................................... 100
6.5 EXTENSION 2FDD MODE (EXT2FDD)................................................................................... 100
7. GENERAL PURPOSE I/O ................................................................................ 101
8. ACPI REGISTERS FEATURES......................................................................... 104
IV
Publication Release Date: Apr. 2000
Revision 0.60