W83L517D Datasheet, PDF (72/138 Pages) Winbond – LPC SUPER I/O

A write to 1 will enable loopback in all modes.
W83L517D
Version 0.6
Bit 3:
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
D_CHSW
DMA Channel Selected
0
Receiver (Default)
1
Transmitter
A write to 1 will enable output data when ALOOP=1.
Bit 2:
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
DMATHL
TX FIFO Threshold
16-Byte
32-Byte
0
13
13
1
23
7
RX FIFO Threshold
(16/32-Byte)
4
10
Bit 1:
DMA_F - DMA Fairness
DMA_F
0
1
Function Description
DMA request (DREQ) is forced inactive after 10.5us
No effect DMA request.
Bit 0:
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
5.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2
Refault Value
1
1
1
0
0
0
Bit 1
SRR1
0
Bit 0
SRR0
0
5.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
65
Bit 3
Bit 2
Bit 1
Bit 0
Publication Release Date: Apr. 2000
Revision 0.60