W83L517D Datasheet, PDF (115/138 Pages) Winbond – LPC SUPER I/O

CR22 (Default 0xFFh)
Bit 7~ 5: Reserved.
Bit 4: Flash I/F Power down
= 0 Power down
= 1 No Power down
Bit 3: FIRPWD
= 0 Power down
= 1 No Power down
Bit 2: URAPWD
= 0 Power down
= 1 No Power down
Bit 1: PRTPWD
= 0 Power down
= 1 No Power down
Bit 0: FDCPWD
= 0 Power down
= 1 No Power down
W83L517D
Version 0.6
CR23 (Default 0x00h)
Bit 7: GPIO 5X Output Mode Selection.
= 0. When on inactive situation, each signal of GPIO 5X will be open-drain.
= 1. When on inactive situation, each signal of GPIO 5X will be 5V CMOS structure.
Bit 6: GPIO 4X Output Mode Selection.
= 0. Each signal of GPIO 4X will be open-drain.
= 1. Each signal of GPIO 4X will be 5V CMOS structure.
Bit 5: GPIO 3X Output Mode Selection.
= 0. When on inactive situation, each signal of GPIO 3X will be open-drain.
= 1. When on inactive situation, each signal of GPIO 3X will be 5V CMOS structure.
Bit 4: GPIO 2X Output Mode Selection.
= 0. When on inactive situation, each signal of GPIO 2X will be open-drain.
= 1. When on inactive situation, each signal of GPIO 2X will be 5V CMOS structure.
Bit 3: GPIO 1X Output Mode Selection.
= 0. When on inactive situation, each signal of GPIO 1X will be open-drain.
= 1. When on inactive situation, each signal of GPIO 1X will be 5V CMOS structure.
Bit 2: Flash ROM I/F Address Segment ( 000F0000h – 000FFFFFh) Enable.
= 0 Enable (Default).
= 1 Disable.
Bit 1: Flash ROM I/F Address Segment ( 000E0000h – 000EFFFFh) Enable.
= 0 Enable (Default).
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Publication Release Date: Apr. 2000
Revision 0.60