W83L517D Datasheet, PDF (79/138 Pages) Winbond – LPC SUPER I/O

Reset
Value
Bit 7~5
W83L517D
Version 0.6
0
0
0
0
0
0
0
0
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR
(Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Bit 4:
Reserved, write 0.
Bit 3:
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allows user to swap DMA channel for transmitter or receiver when flow control is
enforced.
FC_DSW
Next Mode After Flow Control Occurred
0
Receiver Channel
1
Transmitter Channel
Bit 2:
Bit 1:
Bit 0:
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in Set5.Reg1~0) to
be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
5.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SSR
SSR7 SSR6 SSR5 SSR4 SSR3 SSR2 SRR1
Default Value ₁
1
1
0
1
1
0
Bit 0
SRR0
0
5.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IRCFG1 -
Reset Value ₀
FSF_TH FEND_M AUX_RX -
0
0
0
0
Bit 2
-
0
Bit 1
IRHSSL
0
Bit 0
IR_FULL
0
Bit 7:
Bit 6:
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
72
Publication Release Date: Apr. 2000
Revision 0.60