W83L517D Datasheet, PDF (63/138 Pages) Winbond – LPC SUPER I/O

IR FIFO Control Register (UFR):
Mode
Bit 7
Bit 6
Bit 5
Legacy IR RXFTL1 RXFTL0
0
(MSB) (LSB)
Advanced RXFTL1
IR
(MSB)
Reset Value
0
RXFTL0
(LSB)
0
TXFTL1
(MSB)
0
Bit 4
0
TXFTL0
(LSB)
0
W83L517D
Version 0.6
Bit 3
0
Bit 2
Bit 1
Bit 0
TXF_RST RXF_RST EN_FIFO
0 TXF_RST RXF_RST EN_FIFO
0
0
0
0
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
TABLE: FIFO TRIGGER LEVEL
Bit 7
Bit 6
RX FIFO Interrupt Active Level (Bytes)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if UFR
bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
cleared to logical 0 by itself after being set to logical 1.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
cleared to a logical 0 by itself after being set to logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before other
bits of UFR can be programmed.
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Publication Release Date: Apr. 2000
Revision 0.60