W83L517D Datasheet, PDF (80/138 Pages) Winbond – LPC SUPER I/O

W83L517D
Version 0.6
Set this bit to determine the frame status FIFO threshold level and to generate the
FSF_I. The threshold level values are defined as follows.
FSF_TH
0
1
Status FIFO Threshold Level
2
4
Bit 5:
Bit 4:
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Bit 3~2: Reserved, write 0.
Bit 1:
Bit 0:
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates the same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
5.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register shows the bottom byte of frame status FIFO.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
FS_FO FSFDR LST_FR
-
MX_LEX PHY_ERR CRC_ERR RX_OV
Reset Value
0
0
0
0
0
0
0
Bit 0
FSF_OV
0
Bit 7:
FSFDR - Frame Status FIFO Data Ready
Indicates that a data byte is valid in frame status FIFO bottom.
Bit 6:
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Bit 5: Reserved.
Bit 4: MX_LEX - Maximum Frame Length Exceed
73
Publication Release Date: Apr. 2000
Revision 0.60