LM3S5G31 Datasheet, PDF (994/1223 Pages) Texas Instruments – Stellaris LM3S5G31 Microcontroller

Pulse Width Modulator (PWM)
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004
This register provides a method to perform synchronization of the counters in the PWM generation
blocks. Setting a bit in this register causes the specified counter to reset back to 0; setting multiple
bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading
them back as zero indicates that the synchronization has completed.
PWM Time Base Sync (PWMSYNC)
PWM0 base: 0x4002.8000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SYNC2 SYNC1 SYNC0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
Name
reserved
SYNC2
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Reset Generator 2 Counter
Value Description
1 Resets the PWM generator 2 counter.
0 No effect.
1
SYNC1
R/W
0
Reset Generator 1 Counter
Value Description
1 Resets the PWM generator 1 counter.
0 No effect.
0
SYNC0
R/W
0
Reset Generator 0 Counter
Value Description
1 Resets the PWM generator 0 counter.
0 No effect.
994
July 03, 2014
Texas Instruments-Production Data